Sector

IndustrialsSemiconductors

Background

Brinton Johns and Jon Bathgate are investors at NZS Capital. We cover the value chain of semiconductors, the evolution of Cadence and the EDA market, and how Cadence has been able to mitigate the cyclical nature of the industry over the last decade.

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Date

March 2, 2022

Episode Number

49

Cadence Design Systems Business Breakdown

Background / Overview

Cadence Design Systems, formed in 1989 through the merger of ECAD and SDA, is a pivotal player in the electronic design automation (EDA) software market, which is critical for designing integrated circuits (chips). Operating at the intersection of software and hardware, Cadence enables the creation of increasingly complex and powerful semiconductors that power devices from smartphones to cloud infrastructure. Headquartered in San Jose, California, Cadence serves a global customer base, including major tech firms like Apple, NVIDIA, and Amazon, as well as traditional chipmakers like Intel and Texas Instruments. The company employs thousands of engineers and technical staff, reflecting its R&D-intensive nature. Over the past three decades, Cadence has evolved from a niche EDA provider to a mission-critical partner in the $550 billion semiconductor industry, capitalizing on the disaggregation of chip design and manufacturing.

Cadence’s story is one of resilience and reinvention. After facing significant challenges in the mid-2000s, including mismanagement and a near-collapse during the 2008 financial crisis, the company underwent a transformative turnaround under the leadership of Lip-Bu Tan, who served as CEO from 2009. By transitioning to a subscription-based revenue model, refocusing R&D, and expanding into adjacent markets like intellectual property (IP) and emulation, Cadence has achieved consistent growth and reduced its exposure to semiconductor industry cyclicality.

Ownership / Fundraising / Recent Valuation

As of the podcast recording, Cadence is a publicly traded company with a market capitalization of approximately $40 billion. The transcript does not provide details on recent fundraising or private equity transactions, as Cadence has been public since its early days. However, it mentions a failed attempt to go private via KKR during the mid-2000s private equity boom, which coincided with a bid to acquire Mentor Graphics. The company’s stock price fell to below $3 per share during the 2008 financial crisis, reflecting a low point in its valuation. Since then, Cadence has experienced significant multiple expansion, driven by its stable growth, high margins, and reduced cyclicality. The transcript does not specify recent enterprise value (EV) multiples, but the company’s valuation reflects its position as a high-quality software business with predictable cash flows.

Key Products / Services / Value Proposition

Cadence’s core offering is EDA software, which serves as the productivity platform for chip designers, akin to Microsoft Office for knowledge workers or Adobe Suite for creatives. The software enables engineers to design, simulate, verify, and produce blueprints for chips containing billions of transistors, each feature as small as one ten-thousandth the width of a human hair. Beyond EDA software, Cadence has expanded into complementary areas:

1. EDA Software (Core Offering):
• Description: Tools for designing chips, covering the entire design flow from concept to tape-out (final design sent to manufacturing). Includes digital and analog design tools.
• Volume: Used by virtually every chip designer globally, with licenses sold on a per-seat basis.
• Price: Typically tens of thousands of dollars per seat annually, though pricing varies by configuration and customer.
• Revenue/EBITDA: Represents the majority of Cadence’s $3 billion in revenue, with high gross margins typical of software.
2. IP Blocks:
• Description: Off-the-shelf intellectual property (e.g., USB compatibility, audio processing) licensed to simplify chip design. Acquired through M&A, such as Tensilica for high-performance audio.
• Volume: Growing segment, contributing ~15% of revenue.
• Price: Varies by IP type; standardized blocks are more scalable than custom IP.
• Revenue/EBITDA: High-margin, mid-to-high teens growth, additive to core EDA business.
3. Emulation Hardware:
• Description: Server racks for simulating chip designs before manufacturing, ensuring functionality and speeding time-to-market.
• Volume: Used by large customers designing complex chips (e.g., Apple, NVIDIA).
• Price: High-cost, specialized hardware, often bundled with software licenses.
• Revenue/EBITDA: Smaller but growing segment, with lumpier revenue due to hardware sales.

Value Proposition: Cadence’s tools are mission-critical, enabling innovation in chip design while minimizing costly errors (e.g., a failed $10 million photomask). The software’s stickiness, zero churn, and ability to serve both cutting-edge (e.g., 3nm chips) and legacy designs (e.g., analog chips) make it indispensable. By offering a full design flow, IP, and emulation, Cadence reduces complexity for customers, particularly new entrants like systems companies (e.g., Google, Amazon).

Segments and Revenue Model

Cadence operates primarily in three segments:

1. EDA Software: The core business, providing tools for chip design, simulation, and verification.
2. IP Licensing: Licensing standardized IP blocks to streamline chip design.
3. Emulation and Hardware: Providing simulation hardware and related software for pre-manufacturing testing.

Revenue Model: Cadence generates revenue through three-year subscription contracts, recognized ratably over the contract term. Licenses are sold on a per-seat basis, with pricing tailored to the customer’s needs (e.g., number of engineers, design complexity). The subscription model ensures 85-90% recurring revenue, smoothing out lumpiness from design starts. IP licensing provides high-margin, scalable revenue, while emulation hardware sales are lumpier but tied to large, sticky contracts. Revenue follows design starts, with growth driven by increasing chip complexity, new customer logos (e.g., systems companies), and adjacent market expansion (e.g., AI-driven design tools, simulation).

Splits and Mix

• Customer Mix: Cadence serves a diverse customer base, including:
• Systems Companies (e.g., Apple, Amazon, Google): ~45% of revenue, up from 38% a few years ago, reflecting the rise of in-house chip design.
• Traditional Chipmakers (e.g., NVIDIA, Intel, Texas Instruments): Majority of remaining revenue, with Texas Instruments noted for its 76 business units and hundreds of annual design starts.
• Emerging Players: Venture-backed startups and non-tech firms (e.g., Ford exploring chip design).
• Geo Mix: Global customer base, with high teens percent of sales from China, exposing Cadence to geopolitical risks (e.g., Huawei bans).
• Product Mix: ~85% from EDA software, ~15% from IP, with emulation as a smaller but growing contributor.
• End-Market Mix: Spans smartphones ($400 billion market), PCs ($250 billion), cloud infrastructure, automotive, medical devices, and more, reflecting the ubiquity of chips.
• Channel Mix: Direct sales to chip designers, with no significant distribution intermediaries.
• Revenue vs. EBITDA Contribution: Systems companies and IP licensing are higher-margin segments, boosting overall profitability as their share grows.

Mix Shifts:

• Systems Companies: Growing from 38% to 45% of revenue, driven by tech giants entering chip design.
• IP Licensing: Increasing from a negligible share to 15% of revenue, with mid-to-high teens growth.
• Digital vs. Analog: Cadence has gained share in digital design (e.g., NVIDIA, Apple), complementing its historical strength in analog (e.g., Texas Instruments).

KPIs

• Revenue CAGR: Accelerated from mid-to-high single digits 5-6 years ago to 13% over the past three years.
• Operating Margin: High thirties, with potential to reach low-to-mid forties in 5-6 years.
• Free Cash Flow Margin: Low thirties, reflecting high R&D intensity but strong cash conversion.
• Recurring Revenue: 85-90% of revenue, providing predictability.
• Churn: Effectively 0%, as customers rely on Cadence tools unless they exit chip design entirely.
• Design Starts: Correlates with revenue growth, driven by chip complexity and new customer logos.
• Incremental Margin: ~50%, indicating strong operating leverage.

Acceleration/Deceleration: Revenue growth has accelerated due to systems companies, digital design share gains, and IP growth. No signs of deceleration, even through semiconductor cycles.

Headline Financials

Long-Term Financial Trends:

• Revenue: Grew from mid-single digits to 13% CAGR, outpacing the semiconductor industry’s 6-8% growth.
• EBITDA/Operating Margin: Improved from low margins in the 2000s to high thirties, driven by subscription model and operating leverage.
• Free Cash Flow: Consistently strong, with low thirties margins, supporting reinvestment and potential shareholder returns.

Value Chain Position

Cadence operates upstream in the semiconductor value chain, providing the software and IP that enable chip design. The value chain includes:

• Upstream: EDA software (Cadence, Synopsys), IP providers (Arm, Cadence), and simulation tools (Ansys).
• Midstream: Chip design (NVIDIA, Apple) and manufacturing (TSMC, Intel).
• Downstream: Device assembly (Foxconn) and end products (smartphones, PCs, cars).

Primary Activities:

• R&D: Developing EDA tools, IP, and emulation hardware.
• Sales: Direct sales to chip designers, with contracts tailored to design needs.
• Customer Support: Ensuring tools meet customer requirements, critical for stickiness.

Go-To-Market (GTM) Strategy: Cadence sells directly to chip designers, leveraging its reputation and mission-critical role. The subscription model aligns with ongoing design activity, ensuring long-term relationships. Cadence targets both established players (e.g., Intel) and new entrants (e.g., Amazon), capitalizing on the democratization of chip design.

Competitive Advantage: Cadence’s value-add lies in its comprehensive design flow, sticky software (zero churn), and ability to support complex designs (e.g., 3nm chips). Its emulation tools and IP blocks further differentiate it, reducing customer time-to-market and risk.

Customers and Suppliers

• Customers: Diverse, including systems companies (Apple, Amazon, Google), traditional chipmakers (NVIDIA, Intel), and emerging players (VC-backed startups, Ford). No single customer dominates, reducing concentration risk.
• Suppliers: Limited supplier dependency, as Cadence’s primary inputs are engineering talent and computing infrastructure for R&D. IP acquisitions (e.g., Tensilica) reduce reliance on third-party IP providers.

Pricing

• Contract Structure: Three-year subscriptions, recognized ratably, with per-seat pricing (tens of thousands per seat annually).
• Pricing Drivers:
• Mission-Criticality: EDA tools are essential, justifying premium pricing.
• Chip Complexity: Advanced nodes (e.g., 3nm) require more tools and seats, driving revenue.
• Customer Type: Systems companies starting from scratch (e.g., Google) pay more than legacy chipmakers with existing IP.
• Historical Context: Pricing was a headwind in the 2000s due to aggressive customer negotiations but has become a modest tailwind post-subscription model.
• Visibility: High, with 85-90% recurring revenue and three-year contracts.
• GTM: Direct sales, with pricing tailored to design complexity and team size.

Bottoms-Up Drivers

Revenue Model & Drivers

How Cadence Makes $1:

• EDA Software (~85% of Revenue): Sold on a per-seat basis to chip designers. Revenue scales with design starts, team size, and chip complexity (e.g., 3nm vs. 5nm designs).
• IP Licensing (~15% of Revenue): Standardized IP blocks (e.g., USB, audio) licensed to simplify design, with high margins and mid-to-high teens growth.
• Emulation Hardware: Lumpier revenue from server racks for simulation, tied to large contracts with major customers.

Revenue Drivers:

• Volume:
• Design Starts: Correlate with revenue, driven by new products, end markets (e.g., AI, automotive), and customer growth (e.g., Amazon’s chip team expanding from 100 to over 1,000 engineers).
• New Logos: Systems companies (e.g., Google, Ford) and VC-backed startups increase seat demand.
• Industry Growth: Semiconductor R&D (15% of $550 billion industry) grows 6-8%, with EDA capturing 2.25% (~$10 billion TAM).
• Price:
• Modest tailwind post-subscription model, reversing historical declines.
• Driven by value-add (e.g., emulation saves time-to-market) and chip complexity.
• Mix:
• Shift to systems companies (45% of revenue) and IP (15%) boosts margins.
• Digital design share gains complement analog strength.

Absolute Revenue: $3 billion, with 13% CAGR, outpacing industry growth due to new markets and share gains.

Cost Structure & Drivers

Cost Breakdown:

• R&D (35% of Sales): Fixed cost, driven by engineering talent and tool development for next-generation nodes (e.g., 2nm).
• Sales & Marketing: Low relative to growth software, as customers are captive with zero churn.
• COGS: Minimal for software; higher for emulation hardware but a small segment.
• G&A: Standard overhead, benefiting from scale.

Fixed vs. Variable:

• Fixed Costs: R&D and G&A dominate, providing operating leverage as revenue grows.
• Variable Costs: Limited to hardware COGS and minor sales expenses, ensuring high contribution margins.

Operating Leverage: 50% incremental margins reflect fixed-cost scalability. As revenue grows, R&D as a percentage of sales could decline, pushing margins to low-to-mid forties.

EBITDA Margin: High thirties, driven by:

• Revenue growth (13% CAGR).
• Fixed-cost leverage (R&D scales sub-linearly).
• Mix shift to high-margin IP and systems customers.

FCF Drivers

• Net Income: High thirties operating margins translate to strong profitability post-tax.
• Capex: Low, as Cadence is software-driven, with minimal physical infrastructure needs.
• NWC: Stable, with predictable receivables due to subscription model and low inventory.
• Cash Conversion Cycle: Short, as payments are upfront or ratable, with minimal payables.

FCF Margin: Low thirties, reflecting high R&D but strong cash generation. Supports reinvestment in R&D, M&A (e.g., IP acquisitions), and potential shareholder returns.

Capital Deployment

• M&A: Strategic acquisitions (e.g., Tensilica for IP) expand TAM and margins. No overpayment concerns noted.
• Organic Growth: 13% CAGR driven by R&D and market expansion, outpacing inorganic contributions.
• Buybacks/Dividends: Not emphasized, with focus on reinvestment.

Market, Competitive Landscape, Strategy

Market Size and Growth

• EDA Market: ~$10 billion, ~2.25% of the $550 billion semiconductor industry (15% of chip R&D).
• Growth: 6-8% industry growth, with EDA growing faster (13% for Cadence) due to chip complexity, systems companies, and IP/emulation.
• Volume: Driven by design starts, team growth, and new end markets (e.g., AI, automotive).
• Price: Modest tailwind, with value-add justifying stable pricing.

Market Structure

• Oligopoly: Dominated by Cadence (~33% share), Synopsys, and Mentor Graphics (acquired by Siemens). Ansys is a smaller player.
• Barriers to Entry: High, due to 30+ years of expertise, sticky software, and R&D intensity.
• MES (Minimum Efficient Scale): Large, requiring significant scale to compete, limiting new entrants.
• Cyclicality: Low for EDA, as R&D is the last cost cut, unlike memory or equipment.

Competitive Positioning

• Matrix: High-quality, mission-critical software for advanced (digital) and legacy (analog) designs, serving both tech giants and traditional chipmakers.
• Differentiation: Full design flow, IP, emulation, and AI-driven tools. Sticky software with zero churn.
• Risk of Disintermediation: Low, as EDA is only 2% of customer costs but critical.

Market Share & Relative Growth

• Share: ~33% of EDA market, stable vs. Synopsys, with gains in digital design.
• Relative Growth: 13% CAGR vs. 6-8% industry growth, driven by systems companies and IP.

Competitive Forces (Hamilton’s 7 Powers)

1. Economies of Scale: High fixed R&D costs create operating leverage, with 50% incremental margins. Large MES limits competitors.
2. Switching Costs: Extreme, with zero churn. Customers rely on Cadence’s tools for decades, with high costs to switch.
3. Branding: Strong reputation for reliability, critical for $500 million chip designs.
4. Counter-Positioning: Subscription model and IP/emulation add-ons differentiate vs. point-tool providers.
5. Cornered Resource: 30+ years of design expertise and customer relationships.
6. Process Power: AI-driven tools and emulation optimize design efficiency, hard for competitors to replicate.
7. Network Effects: Limited, as EDA is not a platform business.

Porter’s Five Forces:

• New Entrants: Low threat due to high barriers (expertise, R&D, stickiness).
• Substitutes: Low, as no viable alternative to EDA exists (open-source tools are nascent).
• Supplier Power: Low, as Cadence relies on talent and minimal external inputs.
• Buyer Power: Moderate, reduced by subscription model and mission-criticality.
• Rivalry: High but stable, with Cadence and Synopsys dominating.

Strategic Logic

• R&D Investment: 35% of sales ensures Cadence stays ahead of Moore’s Law and supports new applications (e.g., AI, simulation).
• Horizontal Expansion: IP and emulation grow TAM beyond core EDA.
• Customer Proximity: Close collaboration (e.g., with TSMC) ensures tools meet evolving needs.
• M&A: Disciplined acquisitions (e.g., Tensilica) enhance offerings without diluting margins.

Valuation

• Market Cap: ~$40 billion.
• Multiple: High, reflecting low cyclicality, 13% growth, and high thirties margins. Comparable to mature software peers (e.g., Ansys, low forties margins).
• Upside Case: 15% bottom-line growth for 5 years (2x valuation) is high probability. 10x in 5 years is low probability, requiring semiconductor R&D growth to accelerate to mid-teens.
• Bear Case: Geopolitical risks (e.g., China bans, high teens of sales) or open-source disruption (e.g., Google tools) could pressure growth, though unlikely to materially shrink value.

Key Dynamics and Unique Aspects

1. Mission-Criticality and Stickiness:
• Cadence’s EDA tools are indispensable, with zero churn. Customers cannot design chips without them, and switching costs are prohibitive due to decades of integration.
• The software’s role in preventing costly errors (e.g., $10 million photomask failures) justifies premium pricing and ensures customer loyalty.
2. Low Cyclicality:
• Unlike memory or equipment, EDA is insulated from semiconductor cycles, as R&D is the last cost cut. Cadence’s slowest growth was 6% during past cycles, with a 13% CAGR recently.
• The subscription model smooths revenue over three years, enhancing predictability.
3. Democratization of Chip Design:
• The rise of systems companies (e.g., Apple, Amazon) and VC-backed startups has expanded Cadence’s customer base, with systems companies growing from 38% to 45% of revenue.
• New entrants rely heavily on Cadence’s tools and IP, driving seat growth and margins.
4. Adjacent Market Expansion:
• IP licensing (15% of revenue, mid-to-high teens growth) and emulation hardware add high-margin revenue streams, growing TAM beyond the $10 billion EDA market.
• AI-driven tools and simulation (e.g., computational fluid dynamics) position Cadence for future growth as Moore’s Law slows.
5. Operating Leverage:
• High fixed R&D costs (35% of sales) yield 50% incremental margins, with potential for margin expansion to low-to-mid forties as revenue scales.
• Low variable costs and minimal capex enhance free cash flow (low thirties margins).
6. Geopolitical Exposure:
• High teens of sales from China introduce risks, as seen with Huawei bans. Further restrictions could impact growth, though the global semiconductor trend mitigates this.
7. Turnaround Success:
• Lip-Bu Tan’s leadership transformed Cadence from a struggling firm in 2008 (stock < $3) to a $40 billion leader by adopting subscriptions, refocusing R&D, and targeting digital design.
• The subscription model eliminated destructive pricing practices, ensuring stable revenue and pricing tailwinds.

Conclusion

Cadence Design Systems exemplifies a resilient, high-quality business with a unique position in the semiconductor ecosystem. Its EDA software, IP, and emulation tools are mission-critical, enabling the design of chips that power the digital economy. The company’s subscription model, low cyclicality, and operating leverage drive predictable 13% revenue growth and high thirties margins, with strong free cash flow. Strategic expansions into IP and simulation, coupled with the democratization of chip design, position Cadence for continued outperformance. While geopolitical risks and potential open-source threats exist, the company’s 30+ years of expertise, zero churn, and high barriers to entry make it a compelling long-term investment. Cadence creates far more value than it captures, embodying a low-tariff extractor model that aligns with sustainable growth.